There are two basic configurations of parity generator circuits known to the art. One configuration is a parallel circuit which receives a byte of data comprising n bits transmitted over n parallel data transmission leads. This parity circuit uses n-1 exclusive OR gates to generate a single parity bit for each byte of received data. (See "Introduction to Switching Theory and Logical Design" 2nd ed. by F. J. Hill and G. R. Peterson, John Wiley & Sons (1974), FIG. 8.31).
The other parity generator configuration is a serial parity circuit. This circuit receives the n bits comprising a byte of data one bit at a time and generates a single parity bit. This serial parity circuit appends the parity bit to the byte of data in an extra bit position located at the end of the byte. This method requires a parity circuit for each data transmission lead. (See "Introduction to Switching Theory and Logical Design" 3rd ed. by F. J. Hill and G. R. Peterson, John Wiley & Sons (1981), pages 241 to 244.)
The problem with these prior art circuits is that they generate a parity bit on a per byte basis. In an application where numerous bytes of data are transmitted during a data transmission, each single byte of data requires a generated parity bit. This method is uneconomical and inefficient in a data-handling system which simultaneously transmits multiple bytes of data.